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1/17 march 2003 rev. 3.2 m48z2m1y m48z2m1v 5v or 3.3v, 16 mbit (2mb x 8) zeropower ? sram features summary n integrated, ultra low power sram, power-fail control circuit, and batteries n conventional sram operation; unlimited write cycles n 10 years of data retention in the absence of power n automatic power-fail chip deselect and write protection n write protect voltages (v pfd = power-fail deselect voltage): C m48z2m1y: v cc = 4.5 to 5.5v 4.2v v pfd 4.5v C m48z2m1v: v cc = 3.0 to 3.6v 2.8v v pfd 3.0v n batteries are internally isolated until power is applied n pin and function compatible with jedec standard 2mb x 8 srams figure 1. 36-pin, dip module pldip36 (pl) module 36 1
m48z2m1y, m48z2m1v 2/17 table of contents summary description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 3. dip connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 4. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 2. absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 dc and ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 3. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 5. ac testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 4. capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 5. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 6. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 6. address controlled, read mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 7. chip enable or output enable controlled, read mode ac waveforms . . . . . . . . . . . . . . 7 table 7. read mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 write mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 8. write enable controlled, write mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 9. chip enable controlled, write mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 8. write mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 data retention mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 10. power down/up mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 9. power down/up ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 10. power down/up trip points dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 v cc noise and negative going transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 11. supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3/17 m48z2m1y, m48z2m1v summary description the m48z2m1y/v zeropower ? ram is a non- volatile 16,777,216-bit, static ram organized as 2,097,152 words by 8 bits. the device combines two internal lithium batteries, cmos srams and a control circuit in a plastic 36-pin dip, long module. the zeropower ram replaces industry stan- dard srams. it provides the nonvolatility of proms without any requirement for special write timing or limitations on the number of writes that can be performed. figure 2. logic diagram table 1. signal names figure 3. dip connections ai02048 21 a0-a20 w dq0-dq7 v cc m48z2m1y m48z2m1v g v ss 8 e a0-a20 address inputs dq0-dq7 data inputs / outputs e chip enable g output enable w write enable v cc supply voltage v ss ground nc not connected internally v ss v cc ai02049 m48z2m1y m48z2m1v 10 1 2 5 6 7 8 9 11 12 13 16 17 18 30 29 26 25 24 23 22 21 20 19 3 4 28 27 32 31 14 15 34 33 36 35 a1 a0 dq0 a7 a4 a3 a2 a6 a5 a13 a10 a8 a9 dq7 a15 a11 g e dq5 dq1 dq2 dq3 dq4 dq6 a16 a18 a12 a14 w a17 a20 nc nc a19
m48z2m1y, m48z2m1v 4/17 figure 4. block diagram maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect de- vice reliability. refer also to the stmicroelectronics sure program and other rel- evant quality documents. table 2. absolute maximum ratings note: 1. soldering temperature not to exceed 260c for 10 seconds (total thermal budget not to exceed 150c for longer than 30 se conds). caution: negative undershoots below C0.3v are not allowed on any pin while in the battery back-up mode. ai02050 internal batteries e v cc v ss voltage sense and switching circuitry 2048k x 8 sram array a0-a20 dq0-dq7 w g power e symbol parameter value unit t a ambient operating temperature 0 to 70 c t stg storage temperature (v cc off) C40 to 85 c t bias temperature under bias C40 to 85 c t sld (1) lead solder temperature for 10 seconds 260 c v io input or output voltages m48z2m1y C0.3 to 7 v m48z2m1v C0.3 to 4.6 v v cc supply voltage m48z2m1y C0.3 to 7 v m48z2m1v C0.3 to 4.6 v i o output current 20 ma p d power dissipation 1 w
5/17 m48z2m1y, m48z2m1v dc and ac parameters this section summarizes the operating and mea- surement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measure- ment conditions listed in the relevant tables. de- signers should check that the operating conditions in their projects match the measurement condi- tions when using the quoted parameters. table 3. operating and ac measurement conditions note: output hi-z is defined as the point where data is no longer driven. figure 5. ac testing load circuit table 4. capacitance note: 1. effective capacitance measured with power supply at 5v; sampled only, not 100% tested. 2. outputs deselected. 3. at 25c. parameter m48z2m1y m48z2m1v unit supply voltage (v cc ) 4.5 to 5.5 3.0 to 3.6 v ambient operating temperature (t a ) 0 to 70 0 to 70 c load capacitance (c l ) 100 50 pf input rise and fall times 5 5ns input pulse voltages 0 to 3 0 to 3 v input and output timing ref. voltages 1.5 1.5 v ai07816 5v out c l = 100pf or 5pf (y) 50pf or 5pf (v) c l includes jig capacitance 1.9k w device under test 1k w symbol parameter (1,2) min max unit c in input capacitance 40 pf c io (3) input / output capacitance 40 pf
m48z2m1y, m48z2m1v 6/17 table 5. dc characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c; v cc = 4.5 to 5.5v or 3.0 to 3.6v (except where noted). 2. outputs deselected. operation modes the m48z2m1y/v has its own power-fail detect circuit. the control circuitry constantly monitors the single 5v supply for an out of tolerance condi- tion. when v cc is out of tolerance, the circuit write protects the sram, providing a high degree of data security in the midst of unpredictable system operations brought on by low v cc . as v cc falls be- low approximately 3v, the control circuitry con- nects the batteries which sustain data until valid power returns. table 6. operating modes note: x = v ih or v il ; v so = battery back-up switchover voltage. 1. see table 10, page 12 for details. sym parameter test condition (1) m48z2m1y m48z2m1v unit min max min max i li (2) input leakage current 0v v in v cc 4 4 a i lo (2) output leakage current 0v v out v cc 4 4 a i cc supply current e = v il , outputs open 140 50 ma i cc1 supply current (standby) ttl e = v ih 10 2 ma i cc2 supply current (standby) cmos e 3 v cc C 0.2v 81ma v il input low voltage C0.3 0.8 C0.3 0.6 v v ih input high voltage 2.2 v cc + 0.3 2.2 v cc + 0.3 v v ol output low voltage i ol = 2.1ma 0.4 0.4 v v oh output high voltage i oh = C1ma 2.4 2.2 v mode v cc e g w dq0-dq7 power deselect 3.0 to 3.6v or 4.5 to 5.5v v ih x x high z standby write v il x v il d in active read v il v il v ih d out active read v il v ih v ih high z active deselect v so to v pfd (min) (1) x x x high z cmos standby deselect v so (1) x x x high z battery back-up mode
7/17 m48z2m1y, m48z2m1v read mode the m48z2m1y/v is in the read mode whenever w (write enable) is high and e (chip enable) is low. the device architecture allows ripple-through access of data from eight of 16,777,216 locations in the static storage array. thus, the unique ad- dress specified by the 21 address inputs defines which one of the 2,097,152 bytes of data is to be accessed. valid data will be available at the data i/o pins within address access time (t avqv ) after the last address input signal is stable, providing that the e (chip enable) and g (output enable) access times are also satisfied. if the e and g ac- cess times are not met, valid data will be available after the later of chip enable access time (t elqv ) or output enable access time (t glqv ). the state of the eight three-state data i/o signals is con- trolled by e and g . if the outputs are activated be- fore t avqv , the data lines will be driven to an indeterminate state until t avqv . if the address in- puts are changed while e and g remain low, out- put data will remain valid for output data hold time (t axqx ) but will go indeterminate until the next ad- dress access. figure 6. address controlled, read mode ac waveforms note: chip enable (e ) and output enable (g ) = low, write enable (w ) = high. figure 7. chip enable or output enable controlled, read mode ac waveforms note: write enable (w ) = high. ai02051 taxqx data valid a0-a20 dq0-dq7 tavav tavqv ai02052 tavav tavqv taxqx telqv telqx tehqz tglqv tglqx tghqz data out a0-a20 e g dq0-dq7 valid
m48z2m1y, m48z2m1v 8/17 table 7. read mode ac characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c; v cc = 4.5 to 5.5v or 3.0 to 3.6v (except where noted). 2. c l = 100pf or 50pf (see figure 5, page 5). 3. c l = 5pf (see figure 5, page 5). symbol parameter (1) m48z2m1y m48z2m1v unit C70 C85 min max min max t avav read cycle time 70 85 ns t av qv (2) address valid to output valid 70 85 ns t axqx (2) address transition to output transition 5 5 ns t ehqz (3) chip enable high to output hi-z 30 35 ns t elqv (2) chip enable low to output valid 70 85 ns t elqx (3) chip enable low to output transition 5 5 ns t ghqz (3) output enable high to output hi-z 25 35 ns t glqv (2) output enable low to output valid 35 45 ns t glqx (3) output enable low to output transition 5 5 ns
9/17 m48z2m1y, m48z2m1v write mode the m48z2m1y/v is in the write mode whenev- er w and e are active. the start of a write is ref- erenced from the latter occurring falling edge of w or e . a write is terminated by the earlier rising edge of w or e . the addresses must be held valid throughout the cycle. e or w must return high for minimum of t e- hax from e or t whax from w prior to the initiation of another read or write cycle. data-in must be valid t dveh or t dvwh prior to the end of write and remain valid for t ehdx or t whdx afterward. g should be kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on e and g , a low on w will disable the outputs t wlqz after w falls. figure 8. write enable controlled, write mode ac waveforms note: output enable (g ) = high. figure 9. chip enable controlled, write mode ac waveforms note: output enable (g ) = high. ai02053 tavav twhax tdvwh data input a0-a20 e w dq0-dq7 valid tavwh tavel twlwh tavwl twlqz twhdx twhqx ai02054 tavav tehax tdveh a0-a20 e w dq0-dq7 valid taveh tavel tavwl teleh tehdx data input
m48z2m1y, m48z2m1v 10/17 table 8. write mode ac characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c; v cc = 4.5 to 5.5v or 3.0 to 3.6v (except where noted). 2. c l = 5pf (see figure 5, page 5). 3. if e goes low simultaneously with w going low, the outputs remain in the high impedance state. symbol parameter (1) m48z2m1y m48z2m1v unit C70 C85 min max min max t avav write cycle time 70 85 ns t ave h address valid to chip enable high 65 75 ns t av el address valid to chip enable low 0 0 ns t avwh address valid to write enable high 65 75 ns t av wl address valid to write enable low 0 0 ns t dveh input valid to chip enable high 30 35 ns t dvwh input valid to write enable high 30 35 ns t ehax chip enable high to address transition 15 15 ns t ehdx chip enable high to input transition 10 15 ns t eleh chip enable low to chip enable high 55 75 ns t whax write enable high to address transition 5 5 ns t whdx write enable high to input transition 0 0 ns t whqx (2,3) write enable high to output transition 5 5 ns t wlqz (2,3) write enable low to output hi-z 25 30 ns t wlwh write enable pulse width 55 65 ns
11/17 m48z2m1y, m48z2m1v data retention mode with valid v cc applied, the m48z2m1y/v oper- ates as a conventional bytewide? static ram. should the supply voltage decay, the ram will au- tomatically power-fail deselect, write protecting it- self t wp after v cc falls below v pfd . all outputs become high impedance, and all inputs are treated as don't care. if power fail detection occurs during a valid ac- cess, the memory cycle continues to completion. if the memory cycle fails to terminate within the time t wp , write protection takes place. when v cc drops below v so , the control circuit switches power to the internal energy source which preserves data. the internal coin cells will maintain data in the m48z2m1y/v after the initial application of v cc for an accumulated period of at least 10 years when v cc is less than v so . as system power returns and v cc rises above v so , the batteries are dis- connected, and the power supply is switched to external v cc . write protection continues for t er af- ter v cc reaches v pfd to allow for processor stabi- lization. after t er , normal ram operation can resume. for more information on battery storage life refer to the application note an1012. figure 10. power down/up mode ac waveforms ai01031 v cc e (per control input) outputs don't care high-z tf tfb tr trb twp tdr valid valid (per control input) recognized recognized v pfd (max) v pfd (min) v so ter
m48z2m1y, m48z2m1v 12/17 table 9. power down/up ac characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c; v cc = 4.5 to 5.5v or 3.0 to 3.6v (except where noted). 2. v pfd (max) to v pfd (min) fall time of less than tf may result in deselection/write protection not occurring until 200s after v cc pass- es v pfd (min). 3. v pfd (min) to v ss fall time of less than t fb may cause corruption of ram data. table 10. power down/up trip points dc characteristics note: 1. all voltages referenced to v ss . 2. valid for ambient operating temperature: t a = 0 to 70c; v cc = 4.5 to 5.5v or 3.0 to 3.6v (except where noted). 3. at 25c; v cc = 0v. symbol parameter (1) min max unit t er e recovery time 40 120 ms t f (2) v pfd (max) to v pfd (min) v cc fall time 300 s t fb (3) v pfd (min) to v so v cc fall time m48z2m1y 10 s m48z2m1v 150 s t r v pfd (min) to v pfd (max) v cc rise time 10 s t wp write protect time from v cc = v pfd m48z2m1y 40 150 s m48z2m1v 40 250 s symbol parameter (1,2) min typ max unit v pfd power-fail deselect voltage m48z2m1y 4.2 4.3 4.5 v m48z2m1v 2.8 2.9 3.0 v v so battery back-up switchover voltage m48z2m1y 3.0 v m48z2m1v 2.45 v t dr (3) expected data retention time 10 years
13/17 m48z2m1y, m48z2m1v v cc noise and negative going transients i cc transients, including those produced by output switching, can produce voltage fluctuations, re- sulting in spikes on the v cc bus. these transients can be reduced if capacitors are used to store en- ergy which stabilizes the v cc bus. the energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. a ceramic by- pass capacitor value of 0.1f (as shown in figure 11) is recommended in order to provide the need- ed filtering. in addition to transients that are caused by normal sram operation, power cycling can generate neg- ative voltage spikes on v cc that drive it to values below v ss by as much as one volt. these negative spikes can cause data corruption in the sram while in battery backup mode. to protect from these voltage spikes, it is recommended to con- nect a schottky diode from v cc to v ss (cathode connected to v cc , anode to v ss ). schottky diode 1n5817 is recommended for through hole and mbrs120t3 is recommended for surface mount. figure 11. supply voltage protection ai02169 v cc 0.1 m f device v cc v ss
m48z2m1y, m48z2m1v 14/17 package mechanical information figure 12. pldip36 C 36-pin plastic dip long module, package outline note: drawing is not to scale. table 11. pldip36 C 36-pin plastic dip long module, package mechanical data symb mm inches typ min max typ min max a 9.27 9.52 0.3650 0.3748 a1 0.38 0.0150 b 0.43 0.59 0.0169 0.0232 c 0.20 0.33 0.0079 0.0130 d 52.58 53.34 2.0701 2.1000 e 18.03 18.80 0.7098 0.7402 e1 2.30 2.81 0.0906 0.1106 e3 38.86 47.50 1.5300 1.8701 ea 14.99 16.00 0.5902 0.6299 l 3.05 3.81 0.1201 0.1500 s 4.45 5.33 0.1752 0.2098 n36 36 pmdip a1 a l be1 d e n 1 ea e3 s c
15/17 m48z2m1y, m48z2m1v part numbering table 12. ordering information scheme note: 1. contact sales offices for availability of extended temperature. for a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact the st sales office nearest you. example: m48z 2m1y C70 pl 1 device type m48z supply voltage and write protect voltage 2m1y = v cc = 4.5 to 5.5v; v pfd = 4.2 to 4.5v 2m1v = v cc = 3.0 to 3.6v; v pfd = 2.8 to 3.0v speed C70 = 70ns (y) C85 = 85ns (v) package pl = pldip36 temperature range 1 = 0 to 70c 9 (1) = extended temperature shipping method blank = tubes
m48z2m1y, m48z2m1v 16/17 revision history table 13. document revision history date rev. no. revision details july 1999 1.0 first issue 31-aug-00 2.0 from preliminary data to data sheet 20-mar-02 3.0 reformatted; temperature information added to tables (table 4, 5, 7, 8, 9, 10) 29-may-02 3.1 modified v cc noise and negative going transients text 28-mar-03 3.2 remove 5v/5%, add 3v part (figure 2, 3, 5; table 2, 3, 5, 6, 7, 8, 9, 10, 12)
17/17 m48z2m1y, m48z2m1v information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. www.st.com

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